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Research Article
Implementation of Low-Power1-Bit Hybrid Full adder with Reduced Area
G.Arun Kumar1
J. Lokesh2
K. Sudhanshan3
123Department of Computer Science and Engineering, Jayamukhi Institute of Technological Sciences, Warangal, India.
Published Online: March-April 2021
Pages: 11-13
Cite this article
No DOIReferences
1. Inumula Veera Raghava Rao, “Object Tracking and Object Behavior Recognition System in High Dense Crowd Videos for Video
Supervision :A Review”,Jour of Advance Research in Dynamical &Control Systems,Vol.10,2018.
2. M.Zhang,J.Gu,andC.-H.Chang,“A novel hybrid pass logic with static CMOS output drive full-adder cell,” in Proc. Int. Symp. Circuits Syst,
May2003,pp.317–320.
3. A.M.Shams,T.K.Darwish,and M.A.Bayoumi,“Performance analysis of low-power 1-bit CMOS full adder cells,” IEEE Trans. Very Large
Scale Integr.(VLSI)Syst.,vol.10,no.1,pp.20–29,Feb.2002.
4. Inumula Veera Raghava Rao,“A novel image recognition method using multiple component resemblances core synthesis and genetic
algorithm”,IOP Conf. Series: Journal of Physics: Conf. Series 1139 (2018) 012069IOPPublishing.
5. SHARADA M. RANE, SAGAR S. PATHAK,” 4-Bit Full Adder Using1-Bit Hybrid 13 T Adder”,International Research Journal of
Engineering and Technology (IRJET)e-ISSN:2395-0056 Volume:04Issue:05|May
6. -2017.
7. Ram, Shofia, and RoohaRazmidAhamed."Comparison and analysis of combinational circuits using different logic styles",2013Fourth
International Conference on Computing Communications and Networking Technologies(ICCCNT),2013.
Supervision :A Review”,Jour of Advance Research in Dynamical &Control Systems,Vol.10,2018.
2. M.Zhang,J.Gu,andC.-H.Chang,“A novel hybrid pass logic with static CMOS output drive full-adder cell,” in Proc. Int. Symp. Circuits Syst,
May2003,pp.317–320.
3. A.M.Shams,T.K.Darwish,and M.A.Bayoumi,“Performance analysis of low-power 1-bit CMOS full adder cells,” IEEE Trans. Very Large
Scale Integr.(VLSI)Syst.,vol.10,no.1,pp.20–29,Feb.2002.
4. Inumula Veera Raghava Rao,“A novel image recognition method using multiple component resemblances core synthesis and genetic
algorithm”,IOP Conf. Series: Journal of Physics: Conf. Series 1139 (2018) 012069IOPPublishing.
5. SHARADA M. RANE, SAGAR S. PATHAK,” 4-Bit Full Adder Using1-Bit Hybrid 13 T Adder”,International Research Journal of
Engineering and Technology (IRJET)e-ISSN:2395-0056 Volume:04Issue:05|May
6. -2017.
7. Ram, Shofia, and RoohaRazmidAhamed."Comparison and analysis of combinational circuits using different logic styles",2013Fourth
International Conference on Computing Communications and Networking Technologies(ICCCNT),2013.
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