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Testing is a significant early move toward plan of VLSI. With a huge number of semiconductors being coordinated in one chip, various flaws might exist. To precisely and proficiently recognize the shortcoming areas, a solid shape based EPP examination procedure is proposed. The determined rate addresses the EPP of the infused shortcoming. In the circuit, the 3D square upsides of area at the underlying stages are changed and the blunder count is determined. This is finished until the blunder count decreases to nothing. Both the methods are applied to ISCAS '89 benchmark circuits and the boundaries, for example, region, speed and power are registered. It tends to be seen that the region and power are decreased astoundingly by EPP strategy contrasted with FEG technique and the speed increments around by multiple times. The outcomes show that the EPP technique is more beneficial than the diagram based approach. Key Word: adaptation to internal failure, unwavering quality, like lihood based, numerous issue finding.